In recent years, in order to enhance a degree of integration of a memory, there has been proposed a semiconductor memory device (3D semiconductor memory device) in which memory cells are three-dimensionally arranged.
In the 3D semiconductor memory device as described above, a memory block as erase unit is generally larger in size than a planar semiconductor memory device (planar NAND flash memory).
If the block size is larger, interchangeability with the planar semiconductor memory device is difficult to keep and thus a system design of a memory controller needs to be changed. Consequently, the 3D semiconductor memory device needs to be configured such that the memory block as erase unit is made smaller in size.